1. Field of Invention
Embodiments of the invention relate generally to apparatus and methods of generating a time reference. In particular, one embodiment of the invention relates to establishing a time reference for use in a test system.
2. Discussion of Related Art
Time references are employed in a wide variety of systems to provide a reference from which events may be generated and measured. Some examples of systems that employ time references include test systems, computer systems, control systems and distributed systems generally where the distributed system may need to synchronize functions across some distance (e.g., for data collection). Often, computers and other electronic systems distribute a clock signal to various system elements to provide a common time reference. Further, in synchronous systems a synchronous clock is employed as a time reference. For such systems to be effective, the clock must be received at the same time at each of the system elements which employ the clock signal. In practice, however, propagation delays inherent in the transmission medium that is employed (e.g., electrical conductors, optical fibers, etc.) make it difficult to achieve the preceding objective. Further, the propagation delays become an increasing problem for applications that require the measurement and/or timing of relatively fast signals and events (e.g., where events are measured in nanoseconds, picoseconds, etc). That is, ever smaller differences or changes in the transmission time of signals can have a significant impact on system accuracy and performance as measurement speeds increase.
Automatic Test Equipment (“ATE”) that is used to test electronics including electronic circuitry, devices, etc. provides one example where a high degree of precision is required when triggering and measuring the occurrence of events in the system. For example, ATE is often used to test the operation of semiconductors. Generally, during the course of such testing one or more known test signals are applied to stimulate the electronics while one or more measurements are recorded concerning the performance and/or response of the electronics to the test signals at various points in time. The testing of modern circuitry which can operate at very high speeds requires a high degree of resolution and speed in capturing the timing of events, e.g., time measurements in nanoseconds are often required.
Often, the electronics that are undergoing test are connected to one or more instruments included in the ATE system. The instruments may provide a set of connections by which test signals may be applied to an electronics device under test (“DUT”) and response signals may be received from the DUT. An ATE includes multiple signal paths that interconnect the DUT to the various instruments and system controllers. In addition, multiple signal paths also exist between the various instruments. Often, the signal paths between different instruments are routed through a central controller or other device. These signal paths may be of varying lengths.
The plurality of different signal path lengths may effect the accuracy of test measurements because the latency of transmittal signals will vary depending upon the length of the signal path. This problem, is particularly relevant in ATE because of the high resolution of the timing measurements and their relevance to one another.
To date, a variety of approaches have been attempted to reduce or eliminate errors created by signal latency described above. These approaches generally attempt to carefully control and distribute a clock signal throughout the ATE system. Some approaches attempt to do so by more precisely controlling the length of the communication paths. For example, where the ATE includes a plurality of instruments that are connected to a control unit via cables, the length of the cables can be controlled to provide precisely matching cable lengths in an effort to equalize any latency caused as a result of the communication paths. Attempts have also been made to equalize the length of solder traces in systems that employ traces. These approaches, however, may increase system costs significantly, for example, by substantially increasing the cost of the signal cabling and/or associated labor.
Other approaches have attempted to adjust the propagation delay during ATE operation in an attempt to have multiple signals arrive at their destinations at the same time. However, these systems may suffer from too much error. Further, some systems that attempt to control propagation delay do so in a manner that limits the maximum propagation delay that may be compensated for.
Still another approach includes an application specific integrated circuit (ASIC) at each instrument and employs each ASIC to provide a timing reference at each instrument. Sometimes referred to as distributed pattern control, such an approach results in ATE that is more expensive and requires system-wide calibration to confirm that the timing references provided by the various ASICs are synchronized.
In addition, some of the preceding approaches require special fixtures to calibrate the system components to a common time reference, and as a result, require that test heads be undocked to perform such a calibration.